http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-449875-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2000-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ec37243a2fa1e13c5eda8b5b82f95f3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1430663e181a8ca0dadf3971baeb2de5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3727a171602ac1186289cb1cfeb10ad9 |
| publicationDate | 2001-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-449875-B |
| titleOfInvention | Method for forming via hole using retardation layer to reduce overetch |
| abstract | A method uses retardation layer to form the via to reduce the overetch in forming via hole. While forming the via, if the depth of each via hole is different, there will often be an overetch effect. When the overetch occurs on the capacitor electrode, it will roughen the surface and make bad contact between the capacitor and the dielectric plug, and even generate high contact resistance. As for the problem caused by the overetch, a retardation layer is used to overlay the surface of capacitor electrode so as to solve the problem. The retardation layer has a smaller etching speed than the dielectric so that it can reduce the overetch. |
| priorityDate | 2000-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.