http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-439254-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-027 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
| filingDate | 1999-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3db7575b2596b9447484d6deba8ff83e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3dee65a7da10b72e2649ebd786a7ec8 |
| publicationDate | 2001-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-439254-B |
| titleOfInvention | Selector and multilayer interconnection with reduced occupied area on substrate |
| abstract | A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively. The distance between adjacent trunk lines in the same wiring layer is 2d in a connecting area and is d in a non-connecting area. A trunk line in the third wiring layer is branched toward adjacent trunk line, and the branched line is connected through an interlayer contact to a line parallel to a trunk line in the second wiring layer. |
| priorityDate | 1998-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.