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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
filingDate 1998-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2001-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_678e45403ff5a6a01ec6a54ed5bdb8b8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9fc8ad13db4d99e3005b1174d4dddae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7741dceba3a5e079e106e46d0699b0ea
publicationDate 2001-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-421872-B
titleOfInvention Process for forming the plugs with self-aligned contact window
abstract The present invention discloses a process for forming the plugs with self-aligned contact window which includes the following steps: providing a substrate with semiconductor devices; forming a first insulation layer to adaptively cover the semiconductor substrate; sequentially forming a second and a third insulation layer on the first insulation layer; using photolithography process and etching to define a self-aligned contact window exposed on the substrate surface; forming a high temperature doped polysilicon layer on the surface of the third insulation layer and covering the inner wall and the bottom of the self-aligned contact window; forming a low temperature doped polysilicon layer on the high temperature doped polysilicon layer and filling up the self-aligned contact window; conducting a planarization process to remove the excess high temperature doped polysilicon layer and low temperature doped polysilicon layer and also part of the third insulation layer so as to form a plug in the self-aligned contact window.
priorityDate 1998-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 32.