http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-417277-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-00 |
| filingDate | 1999-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a2c634637d81adb44463d820211d07f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00fca0710a551dd94cbedaea24af5b6c |
| publicationDate | 2001-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-417277-B |
| titleOfInvention | Semiconductor apparatus and the manufacture method thereof |
| abstract | The purpose of this invention is to provide a semiconductor apparatus and the manufacture method thereof which will never cause the increase of the manufacture steps and further speed up the DRAM cell and the logic circuit. The method is to design the space of the gate 32a, 32b of the transistor QM of the MOS transistor of the neighboring memory cell into larger space than that of the gate 32c, 32d located outside. Through this, the space insulating film 37 is covered on the n type diffusion layer 34a connected with the capacitor node 24 and the n type diffusion layer 34b connected with the bitline 5. Besides, the first transistor on the memory cell array portion is only to form the silicide film on the source region, drain diffusion layer and the gate surface on the gate, whereas the second transistor on the logic circuit portion is only to form the silicide film on the surface of the source, drain diffusion layer as well as the gate. |
| priorityDate | 1998-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.