http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-416110-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f063b8222ec3c8e746a415e7f364473 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5ad8a37a24718df64d141eb0dd1a0372 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4ddcb273a108a5d8472b335280098e06 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31 |
| filingDate | 1999-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f38c7c53587c06aaa2fd4ba434d945d6 |
| publicationDate | 2000-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-416110-B |
| titleOfInvention | Improved polycide gate manufacturing process capable of decreasing the interface trap |
| abstract | The present invention discloses an improved polycide gate manufacturing process, which primarily decreases the deposition temperature of DCS-WSix, and utilizes additional fluorine content to decrease the interface trap without increasing the thickness of the oxide layer. The present improved manufacturing process comprises the steps of: (a) forming a thin oxide layer on the surface of a semiconductor substrate; (b) depositing a polysilicon layer on the thin oxide layer; (c) using chemical vapor phase deposition method to deposit a WSix layer on the polysilicon layer with WF6 and SiH2Cl2 at a reaction temperature lower than 500 DEG C; and (d) defining the WSix layer, polysilicon layer, and thin oxide layer to form a polycide gate structure. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7544616-B2 |
| priorityDate | 1999-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.