http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-412832-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b2d32a1324eb3a240649ffee8d475d63 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-70 |
| filingDate | 1998-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6aca843f252788457660396f5894af88 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2be38009f31083c5355b7e3873e8e383 |
| publicationDate | 2000-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-412832-B |
| titleOfInvention | Method of forming capacitor in IC |
| abstract | The present invention relates to a method of forming a capacitor in an IC, which comprises sequentially depositing a first dielectric layer and an etch stop layer and exposing a memory cell contact; forming a first polysilicon layer filling up said memory cell contact; forming a second polysilicon layer having a rough surface; orming a first hard mask on the second polysilicon layer, the first hard mask having a thickness of 100 to 300 angstroms; defining an initial pattern of the lower electrode plate of the capacitor; forming a third polysilicon layer having a rough surface; defining the third polysilicon layer by a photolithography and an etching technique to form the lower electrode plate of the capacitor. |
| priorityDate | 1998-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.