http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-410322-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0426 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
| filingDate | 1999-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b19857fefa7c5ad3126276b795aa3d1 |
| publicationDate | 2000-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-410322-B |
| titleOfInvention | Liquid crystal display having dual shift clock wire |
| abstract | Disclosed is an LCD including an LCD panel having a plurality of data lines, a plurality of gate lines intersecting the data lines in a substantially perpendicular state, and a plurality of pixel electrodes arranged in a matrix configuration and each having a switch connected to one of the gate lines and one of the data lines; a gate driver for successively applying a gate voltage to the gate lines to control the switches to ON; a data driver for applying a gray voltage, corresponding to image data signals, to the data lines; and a printed circuit board having a timing controller for generating both the image data signals output to the data driver and a shift clock signal which shifts the image data signals, a first signal wire through which the shift clock signal is transmitted, and a second signal wire through which a first clock signal having a frequency equal to and a phase difference of 90 to 270 DEG compared to the shift clock signal. In another aspect, the printed circuit board has a timing controller for generating first and second image data signals and generating first and second shift clock signals having a phase difference of between 90 and 270 DEG and which respectively shift the first and second image data signals, first and second image data signal wires through which the first and second image data signals are respectively transmitted, and first and second shift clock signal wires through which the first and second shift clock signals are respectively transmitted. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7746315-B2 |
| priorityDate | 1999-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 57.