http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-406395-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_57341227c065dbddd1d3cf801bbaa86a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate | 1998-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_de33c67f50471bcec44f1d0a45c26518 |
| publicationDate | 2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-406395-B |
| titleOfInvention | Method of manufacturing improved polysilicon plug structure |
| abstract | This invention relates to process of forming the improved polysilicon plug structure; said structure connects the bit line structure in the semiconductor device to the source and drain region located in the lower region of the transferring gate transistor. The characteristic of said process is to form the double-shaped opening in the insulated layer, which comprises the narrow lower opening and the wide upper opening; said narrow lower opening is exposed on the top surface of the source and drain. The deposition and the etching pattern of the polysilicon leads to the formation of said improved polysilicon plug structure, which includes the wide concave manager shape with polysilicon being packed-up on the upper-opening of said insulated layer, and the narrow polysilicon plug on the lower-opening of said insulated layer, and said narrow polysilicon plug is in contact with the lower source and drain region. Then an upper bit line structure is formed connecting to the top surface of the concave manager shape packed with polysilicon. |
| priorityDate | 1998-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.