| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-095 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-38 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G03F7-095 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G03F7-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
1998-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c63b2217a6e5a9150b204393a03be77
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cc125a64842b94689f039e8d956052fd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_58c55c8a433fde54e93d7037d48817a8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a7137220a377d67aedb2ea0222c9fc8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d1d3f0fd551290481f69d3ae06d1d30a |
| publicationDate |
2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-406374-B |
| titleOfInvention |
Method for forming transistors with raised source and drains and device formed thereby |
| abstract |
The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps. |
| priorityDate |
1997-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |