http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-398077-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-118 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-118 |
| filingDate | 1997-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_76592b633055a5b3149c8996b3715856 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c2ff6f8429728b400871796af45e046 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b20b85ce7988d59e449714ffdfea59b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97a13ec567a96979b94a81bc7d0b1e6b |
| publicationDate | 2000-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-398077-B |
| titleOfInvention | Semiconductor integrated circuit device |
| abstract | This invention aims to solve unavailable line area due to horizontally allocated line lattice by the first A1 in the construction of macro unit of gate arrays in logic circuit. Low resistive Si-Al material layer is formed via the source-drain area of PMOS transistor and NMOS transistor. By substituting some first A1 partially used as unit of inner wiring, it proceeds with the interconnection among transistors. This kind of method can set wiring region on the spare area of the top of the Si-Al material layer; therefore, the chip allocation flexibility can be increased. |
| priorityDate | 1997-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.