http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-396417-B

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fb7561931131a5fe76f6eb2d2cccb069
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
filingDate 1998-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2000-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1a64d18b91a2e421131f29fe3bf5e6a
publicationDate 2000-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-396417-B
titleOfInvention Method for the formation of a deep-submicron CMOS with self-aligneded silicide contact and extended source/drain contact
abstract This is an oxide layer and a poly-silicon layer on the substrate. Then, a silicon nitride layer is formed on the poly- silicon layer. Furthermore, etching is proceeded on the undoped poly-silicon layer, silicon nitride layer, and oxide layer to form a poly- silicon gate with very short channels. Then thermal annealing is applied to repair damages on the substrate resulted from etching; a pad oxide layer is formed between the poly-silicon gate and the substrate. First, an N-doped amorphous silicon layer is formed on the gate structure and the pad oxide layer, then, source/drain is formed by ion implantation. The N-doped amorphous silicon layer is then transformed into N-doped thermal silica layer. A very shallow extended source/drain contact adjacent to the gate structure is formed simultaneously by using the amorphous silicon layer as a diffusion source. Then the N-doped silica layer is etched back to form a spacer wall. After the shield silicon nitride layer is removed, mental silicide contact can be obtained.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101866844-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101866844-B
priorityDate 1998-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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