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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8249
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
filingDate 1998-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2000-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c75c21c40726b89dd004ff9ea25d07d7
publicationDate 2000-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-392331-B
titleOfInvention Method of fabricating a semiconductor integrated circuit device
abstract In a Bi-CMOS integrated circuit device, to reduce a collector-substrate junction capacitance in an NPN transistor and to reduce the step of forming an anti-punch-through layer of the N-channel MOS transistor. Using as a mask a resist pattern having windows made on an element isolation LOCOS film 113a, 113c and P-type well layer 106, impurities are ion-implanted to form a channel stopper layer 115a, 115b for element isolation of a NPN transistor and an anti-punch-through layer 115c for a N-channel MOS transistor. Thus, a sufficient element isolation withstand voltage can be assured while avoiding an increase in the collector-substrate capacitance of the NPN transistor which is due to the transverse diffusion of the channel stopper layer when an epitaxial layer, well layer and LOCOS film are formed. In addition, without increasing the number of steps, the drain-source withstand voltage of the N-channel type MOS transistor and the short channel durability can be improved.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I426567-B
priorityDate 1997-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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