http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-386312-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 1998-05-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0be7fb9100a1a26a883e04656125c570 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77ba52478a6f02ff13b1ce0e05144a23 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e91eb0496c75af451aa784f903a1638c |
| publicationDate | 2000-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-386312-B |
| titleOfInvention | Vertical split gate flash memory structure and production method therefor |
| abstract | The present invention provides a vertical split gate flash memory structure and a production method thereof. The objective of the present invention is to increase the packing density and solve the problem of misalignment of two layers of polysilicon of the gate electrode. Furthermore, the floating gate memory structure of the present invention at least comprises: a plurality of trenches where each trench is used to form a control gate, a floating gate plate and a vertical channel; a mutually connected first source/drain region on the lower surface of a plurality of trenches, and second source/drain region below the upper surface of the wafer, segregated with a plurality of trenches. A plurality of lateral spacers are located in pairs on the two sides of plural trenches protruded on the surface portion of a wafer. The sidewalls of the trenches have a vertical channel. The bottom and the sidewalls of the trenches have a first dielectric layer therein. The floating gate is located on the first dielectric layer on the bottom of the trench, the second dielectric layer, and the control gate (polysilicon) are sequentially formed on the first dielectric layer of the floating gate and the sidewalls of the trenches. The present invention also provides a method of producing such a device. |
| priorityDate | 1998-05-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.