http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-383467-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 1998-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c13aa3f79f2d9dad5fef54e5d66533d0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c64f08e952970cd39508602c2498b325 |
| publicationDate | 2000-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-383467-B |
| titleOfInvention | Manufacturing method for simplifying embedded DRAM processing |
| abstract | A kind of manufacturing method for simplifying embedded DRAM processing includes the following steps : forming gate respectively on a logic circuit area and a memory area on the substrate and proceeding lightly ion doping process; forming an insulation layer on the substrate; defining the insulation layer; covering photoresist on the insulation layer in memory area with a mask; and proceeding etching step to form an insulation spacer in logic circuit and an insulation layer in memory area; then, applying a self-aligned metal silicide process on logic circuit area. Therefore, it does not need to process spacer etching and form metal silicide in the memory area so as to avoid the device damage in memory area caused by spacer etching using plasma and simplify the heavy ion doping process to shorten the processing time. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104368994-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104368994-B |
| priorityDate | 1998-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.