http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-379446-B

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
filingDate 1998-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2000-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_506c189b8955c1062617cdd37153866b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d1f90cb7b1d361add0c9a6d570615a3
publicationDate 2000-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-379446-B
titleOfInvention Method of manufacturing embedded DRAMs
abstract The present invention provides the method of manufacturing embedded DRAMs by making the surface of the memory circuit region and the surface of the logic circuit region at the same height, increasing thus the planarization of the IC. The invention provides a manufacturing process by leaving in the contact vent of height-length-width ratio fusion resistant metal oxide and using hydrogen plasma for processing or hydrogen heat treatment for changing the fusion resistant metal oxide remaining in the contact vent of the conductivity from nonconductor to conductor. Thus, the fusion resistant metal oxide left in the height-length-width contact vent can be partly selected by using hydrogen plasma treatment or hydrogen heat treatment. The treated part of the fusion resistant metal oxide is converted into conductor as contact connection and the untreated part of fusion resistant metal oxide shall remain as insulator for the dielectric layer of the DRAM capacitor.
priorityDate 1998-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 24.