http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-322623-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 |
| filingDate | 1996-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1997-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a398b3dc116dd01f214736086a812dee http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7741dceba3a5e079e106e46d0699b0ea http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a38fbc267148c4fcf0a791671fac6e1 |
| publicationDate | 1997-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-322623-B |
| titleOfInvention | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells |
| abstract | An integrated process for forming a 4T SRAM and a floating gate memory, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a floating gate over a field oxide region in a second memory region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates, except over the floating gate in the second memory region, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a control gate over the floating gate, and to form a load resistor for the SRAM. |
| priorityDate | 1996-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.