http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-320759-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_57341227c065dbddd1d3cf801bbaa86a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-70 |
| filingDate | 1996-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1997-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_244ec9ef9ac15414a37eabe9f959967b |
| publicationDate | 1997-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-320759-B |
| titleOfInvention | Manufacturing method of memory cell by chemical mechanical polishing technology |
| abstract | A manufacturing method of conductor structure of integrated circuit comprises: (1) on semiconductor wafer depositing one first dielectric, and planarizing the above first dielectric; (2) by lithography and etch technology etching the above first dielectric to expose the above semiconductor wafer to form hole; (3) depositing one first conductor, which fills the above hole; (4) depositing one second dielectric, and by lithography and etch technology etching the above second dielectric above the above hole to form first opening; (5) depositing one third dielectric; (6) by plasma etch technology performing etch back to the above third dielectric so as to form third dielectric spacer on two sides of the above first opening; (7) with the above second dielectric and third dielectric spacer as etching mask, etching the above first conductor to one proper depth so as to form trench on the above first conductor surface above the above hole; (8) removing the above second dielectric; (9) forming one photoresist, which fills the above trench; (10) to the above photoresist performing blanket exposure; (11) removing the above exposed photoresist except the above trench, and in the above trench reserving the above un-exposed photoresist; (12) with photoresist in the above trench and third dielectric spacer as etching mask, by etch technology etching the above first conductor except hole region; (13) removing the above third dielectric spacer and photoresist in the above trench. |
| priorityDate | 1996-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.