http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-314647-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_57341227c065dbddd1d3cf801bbaa86a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate | 1996-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1997-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_244ec9ef9ac15414a37eabe9f959967b |
| publicationDate | 1997-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-314647-B |
| titleOfInvention | Manufacturing method of memory with decreased memory cell layout area |
| abstract | A method of forming polysilicon structure of integrated circuit comprises of the following steps: (1) on semiconductor wafer forming first dielectric, second dielectric and third dielectric, and planarizing the above second dielectric; (2) by lithography and etch technique etching the above first dielectric, second dielectric and third dielectric to form hole; (3) forming one first polysilicon, which filling the above hole; (4) by etch technique conducting etchback to the above first polysilicon, in which the above etch etches the above first polysilicon except the above hole region, and only in the above hole reserving the above first polysilicon to form first polysilicon plug; (5) oxidizing one portion of the above first polysilicon plug in the above hole to form polysilicon oxide, in which one portion of the above polysilicon oxide leaves in the above hole, one portion extrudes the above third dielectric; (6) removing the above third dielectric to expose the above polysilicon oxide and one portion of left the above first polysilicon plug; (7) forming one second polysilicon; (8) by etch technique conducting etchback to the above second polysilicon, so as to form second polysilicon spacer on the above polysilicon oxide and exposed side of the above first polysilicon plug; (9) removing the above polysilicon oxide, leaving the above first polysilicon and second polysilicon spacer to become shell shape with the above hole as symmetric center. |
| priorityDate | 1996-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.