http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-311265-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate | 1996-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1997-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46874f929b369d57f49502f8fe3c62e5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c61aaa6b84a8dc609a598abcdcd28c8f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c036c24b7b56436fe31a01c235b32e1e |
| publicationDate | 1997-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-311265-B |
| titleOfInvention | Manufacturing method of packing logic on same semiconductor chip and single-level polysilicon dynamic random access memory |
| abstract | A method of integrating memory and logic circuit on one single semiconductorsubstrate comprises of the following steps: (1) on the semiconductor substrate forming one oxide field on area prearranged as memory cell and area prearranged as logic circuit;(2) by ion implantation implanting first conductive doped ion in first region on the semiconductor substrate as memory cell, and used to adjust threshold voltage of the memory cell; (3) by ion implantation implanting second conductive doped ion in second region on the semiconductor substrate as one first-type logic device of the logic circuit, and used to adjust threshold voltage of the first-type logic device; (4) one semiconductor substrate growing first insulator; (5) by ion implantation implanting third conductive doped ion in the first region on the semiconductor substrate as memory cell, and to form second part of silicon memory capacitor; (6) on the silicon memory capacitor surface growing second insulator; (7) depositing one polysilicon; (8) doping the polysilicon; (9) implanting the polysilicon, so as to form polysilicon storage gate structure used to the memory cell on the second insulator and form polysilicon converting gate structure on the first insulator, but on the first insulator forming polysilicon gate structure used in the first-type logic device and the second-type logic device; (10) by ion implantation implanting fifth conductive doped ion in first region on the semiconductor substrate first region where is not overlaid by the oxide, the polysilicon storage gate structure and the polysilicon converting gate structure, and the semiconductor substrate will be used as first-type logic device of the logic circuit, and the second area where is not overlaid by the oxide and the polysilicon gate structure is used to form lightly doped source and drain region used in the first-type logic device; (11) by ion implantation implanting sixth conductive doped ion in first region on the semiconductor substrate as second-type logic device of the logic circuit, and the second area where is not overlaid by the oxide and the polysilicon gate structure is used to form lightly doped source and drain region of the second-type logic device; (12) depositing one third insulator; (13) anisotropically etching the third insulator, so as to form insulating sidewall space on the polysilicon storage gate structure side, the polysilicon converging gate structure side and the polysilicon gate structure side; (14) by ion implantation implanting seventh conductive doped ion in first region on the semiconductor substrate, which will be used on first region between the polysilicon converting gate structure and the memory cell, and implanting on the semiconductor substrate which will be used on the first-type logic device, and the second area where is not overlaid by the oxide, the polysilicon gate structure and the insulating sidewall spacer is used to form heavily doped source and drain region used in the first-type logic device; (15) by ion implantation implanting eighth conductive doped ion in first region on the semiconductor substrate which will be used on the second-type logic device, and the second area where is not overlaid by the oxide, the polysilicon gate structure and the insulating sidewall spacer is used to form heavily doped source and drain region of the second-type logic device; (16) depositing one fourth insulator; (17) planarizing the fourth insulator; (18) performing contact opening to the fourth insulator, semiconductor substrate first region between the polysilicon converting gate structure and heavily doped source and drain region of the first-type and the second-type logic device; (19) depositing one metal layer; (20) forming metal contact structure to semiconductor substrate first region between the polysilicon converting gate structure and heavily doped source and drain region of the first-type and the second-type logic device. |
| priorityDate | 1996-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.