http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-304305-B

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-13
filingDate 1995-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1997-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5274aa4cb0d908467d110ce57e9d6071
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_547cd9a487dd92cf72feeead413591da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89fbd9a8c55e04ad70c5d9df2f7a742b
publicationDate 1997-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-304305-B
titleOfInvention The process of vertical bottom gate polysilicon thin film transistors
abstract A process of vertical bottom gate polysilicon thin film transistors with following steps: Provide a SiO2 insulated layer; Deposit polysilicon on SiO2 insulated layer as bottom gate; Etch both sides of bottom gate polysilicon down to SiO2 insulated layer; Deposit a TEOS layer on top surface and side wall of bottom gate polysilicon as gate dielectric; Deposit a non-doped polysilicon layer on bottom gate polysilicon and SiO2 insulated layer as source, drain, offset and active channel; Deposit a pad oxide, and form drain on both ends of bottom gate and form source on top end of polysilicon by ion implantation; Deposit an insulated layer and etch the position of contact window; Deposit a metal Al layer and etch metal contact window; Hydrogenated the product in 300 deg.C H2 plasma.
priorityDate 1995-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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