http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-304292-B

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-70
filingDate 1996-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1997-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2662c3f4541c28b8935ca6ade49e9ce4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c036c24b7b56436fe31a01c235b32e1e
publicationDate 1997-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-304292-B
titleOfInvention The manufacturing method for stacked cylindrical capacitor
abstract A manufacturing method for stacked DRAM, it includes: Form oxide on Si semiconductor substrate as isolated field transistor;Form field transistor and word line, in which the field transistor has gate oxide, gate and source/drain; Form 1st and 2nd dielectric; Etch 1st and 2nd dielectric and expose source of field transistor to form cell contact; Side etching part of 1st dielectric to undercut 1st dielectric under 2nd dielectric; Form 1st polysilicon to fill cell contact; Proceed vertical one-way etching back on 1st polysilicon to form polysilicon plug inside the cell contact; Form 3rd dielectric; Etch 3rd dielectric to form cylindrical contact; Form thin 2nd polysilicon and 4th dielectric then proceed etching back on 4th dielectric to form dielectric plug inside the cylindrical contact; Proceed etching back on thin polysilicon to remove 2nd polysilicon and form polysilicon cylinder on side of cylindrical contact; Remove 3rd dielectric and dielectric plug to form cylindrical storage node;Form transistor dielectric and 3rd polysilicon, and etch 3rd polysilicon andtransistor dielectric to form plate electrode of transistor.
priorityDate 1996-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 31.