http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202215063-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2217-0072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2217-0063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-017
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F3-2171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-017
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2856
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2644
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-6871
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
filingDate 2021-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c590594d95f89db4db3508f4bfe9692b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98a18c0ef8adfa918c201f9c1ac1575f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53a1c4fcf706dda08d7bb5e55a845065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_28a01c141827127101e0ee4c7326e613
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8c09e14d6f1d47381d5b0e859d8895e8
publicationDate 2022-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-202215063-A
titleOfInvention A stacked ganfet reliability built-in self test (bist) apparatus, bist circuit and method
abstract An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.
priorityDate 2020-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559169
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID117559

Total number of triples: 29.