http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202145493-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_54063f3bf0907634a129e16c897d1717 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-49111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48472 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-29 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-52 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538 |
| filingDate | 2021-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d8f522127003f6025ee14b00d1054f95 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77eed15b786256a76aeab03865777931 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9073226ded61f691fb6243f141a15f7d |
| publicationDate | 2021-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-202145493-A |
| titleOfInvention | Semiconductor device |
| abstract | An object of the present invention is to improve the connection reliability of the solder alloy layer interposed between the semiconductor chip and the chip connection portion.nThe semiconductor device 100 of the present invention includes a semiconductor wafer 10 , a conductor pattern 32A, a solder alloy layer 40 and an intermetallic compound layer 50 . The conductor pattern 32A includes metal (eg, Cu), and is connected to the lower surface 10b of the semiconductor wafer 10 via the solder alloy layer 40 . The intermetallic compound layer 50 is formed on the boundary between the lower surface 10b of the semiconductor wafer 10 and the solder alloy layer 40, and has a concavo-convex surface from the lower surface 10b side to the conductor pattern 32A side. The lower surface 10b of the semiconductor wafer 10 includes a first region including the center of the lower surface 10b and a second region including the outer periphery of the lower surface 10b. As shown in FIG. 2, the thickness of the intermetallic compound layer 50, the average thickness of the portion 50R1 overlapping with the first region of the lower surface 10b is thicker than the average thickness of the portion 50R2 overlapping with the second region. |
| priorityDate | 2020-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.