| abstract |
Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures. |