http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202134895-A

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filingDate 2021-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afae695b4eeb4c99ab2375b134442b80
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publicationDate 2021-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-202134895-A
titleOfInvention Memory device and method of operating the same
abstract A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock signal, receiving a first precharge command through the row pins during a first 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second 1 cycle of the clock signal, and receiving a second precharge command through the row pins during a second 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
priorityDate 2020-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 22.