| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-43
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate |
2021-02-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f29f27e99003eeae44782a2b894bec7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7dc77c2df9fd0bd13736ddce846ce26c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e8f0530e3628332e763bc7f0f5c0a06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5324c3c2c4c43ae56fc8f8bc628d94ae |
| publicationDate |
2021-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202133446-A |
| titleOfInvention |
Method for manufacturing semiconductor device |
| abstract |
A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers. |
| priorityDate |
2020-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |