http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202131207-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_39094f1396998763fb81ce213ed520bd |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00013 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-027 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-602 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-64 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-122 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-72 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-76 |
| filingDate | 2020-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b89270af92eed3249fc50496416b5ea5 |
| publicationDate | 2021-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-202131207-A |
| titleOfInvention | Secure integrated circuit |
| abstract | A secure IC includes multiple functionally-equivalent combinational logic circuits, multiple sets of state-sampling components, and control circuitry. Each combinational logic circuit receives one or more inputs, and applies a combinational-logic operation to the one or more inputs so as to produce one or more outputs. Each set of state-sampling components includes one or more state-sampling components that samples one or more of the outputs of one of the combinational logic circuits and provides one or more of the sampled outputs as inputs to another of the combinational logic circuits. The control circuitry receives multiple sets of input data for processing by the combinational logic circuits, routes the sets of input data to the combinational logic circuits, extracts sets of output data from the combinational logic circuits, and outputs each set of output data in association with the respective set of input data. |
| priorityDate | 2020-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 57.