| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2020-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a5df61bb84ef637d7f5af4f8baa87f5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4484247963163cff69c0262a54dfed8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2eb2fc93416ca74a6eb4b101624b6312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0818a3fe7837f2e02467ebdc9ccfdf22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bea47b3a000a98b0e3f2885cf886c51a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4fc0025682c8adb27c90d36fb33f1e1a |
| publicationDate |
2021-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202125830-A |
| titleOfInvention |
Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact |
| abstract |
Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I806183-B |
| priorityDate |
2019-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |