Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fa907cbef2178b7f30a042518be6b17b |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-1204 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-56 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2896 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-1201 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3183 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R19-0092 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-08 |
filingDate |
2019-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_000fd3b6df884969ff90c652a92d50c9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd2b6151a977a85664805af18f0e80e3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aba3cf6b80bc85db8bf3e26530ceb3fa |
publicationDate |
2021-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-202115737-A |
titleOfInvention |
Cell current measurement method for three-dimensional memory |
abstract |
A method for measuring memory cell current of a 3D memory, the method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source line of a 3D memory array of the 3D memory device, and the peripheral circuit formed on a first substrate and the 3D memory array formed on a second substrate are electrically connected by direct bonding. The method further includes applying a second test voltage to bit line pads of the 3D memory array, wherein the bit line pads and the 3D memory array are formed on opposite sides of the second substrate. In some embodiments, the method includes applying a second test voltage to a power pad, wherein the power pad is electrically connected to a page buffer of a peripheral circuit. |
priorityDate |
2019-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |