http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202114114-A

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publicationDate 2021-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-202114114-A
titleOfInvention 1d vertical edge blocking (veb) via and plug
abstract Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I803140-B
priorityDate 2019-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 38.