http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202105392-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_58054227722081749d7e8e121924a5c8 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-882 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 |
| filingDate | 2019-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d6254541eeeae5ee2a05d64467a10259 |
| publicationDate | 2021-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-202105392-A |
| titleOfInvention | Non-volatile semiconductor memory device and manufacturing method thereof |
| abstract | According to the embodiment, the non-volatile semiconductor memory device includes: a first wiring layer extending in a first direction and arranged in a second direction; and a second wiring layer extending in a second direction above the first wiring layer Arranged in the first direction; and the third wiring layer, which extends in the first direction above the second wiring layer, and is arranged in the second direction; and the first memory cell is arranged at the intersection of the second wiring layer and the first wiring layer Part; and the second memory cell, which is arranged at the intersection of the third wiring layer and the second wiring layer; and the third memory cell, which is arranged on the first wiring layer where the first memory cell is arranged is the nearest other A first wiring layer and a second wiring layer; and an insulating layer, which is arranged between the first and third memory cells. The second wiring layer has a laminated structure of two or more layers of different materials. |
| priorityDate | 2019-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.