| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-85
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate |
2020-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f35eaeba96918695e49eedb89a1537d0 |
| publicationDate |
2020-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202040752-A |
| titleOfInvention |
Methods of manufacturing integrated circuit devices |
| abstract |
Methods of manufacturing an integrated circuit device are provided. A method of manufacturing an integrated circuit device includes sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening and a second mask layer having a second opening as an etch mask, respectively. The method includes forming a first wiring recess passing through the wiring insulating layer and a second wiring recess having a depth that is less than that of the first wiring recess by removing a portion of the wiring insulation layer by using a portion of the hard mask layer as an etching mask. Moreover, the method includes forming a wiring structure that is in the first wiring recess and the second wiring recess. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I802474-B |
| priorityDate |
2019-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |