http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202030979-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_31da94917d1067c89f7e22444c88a836 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-1215 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-0624 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-1245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-0836 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-1215 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12 |
| filingDate | 2019-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_71d947e9a8a7b05018fd4762348d6a49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da41e3ceae4505a7b468b84c72d6a63f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e6791dfa99957c7476655d87df69c3f3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7e062468c1b41daac16494eb57bf00e |
| publicationDate | 2020-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-202030979-A |
| titleOfInvention | Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods |
| abstract | Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), where the pulse rate of CLK1 is slower than that of the CLK0 and greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLK1 based on CLK1 and N-phases of the CLK0 and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods. |
| priorityDate | 2018-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 42.