| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_921d8ab3ccc15406e49839c274d4e7d4 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0738
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0865 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7806
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41725
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-048
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-30 |
| filingDate |
2019-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e105938a030c25d0b3808bcb6ed3d5ce |
| publicationDate |
2020-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202017016-A |
| titleOfInvention |
Silicon carbide metal oxide semiconductor field effect transistor with source ballast |
| abstract |
An intergrated device and a method for making said intergrated device. The intergrated device includes a plurality of planar MOSFETs that have a first contact region formed in a first source region of a plurality of source regions and a second contact region formed in a second source region of the plurality of source regions. The first and second contact regions have respective portions of the source region doped with the second conductivity type, and the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other and the first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region. |
| priorityDate |
2018-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |