| abstract |
A memory die of a memory device includes a first-in, first-out circuit, which samples data output from the memory cell array and outputs the data to the buffer die through a first silicon via based on a control signal transmitted from the buffer die. The buffer chip of the memory device includes a second-in-first-out circuit, a calibration circuit, and a delay control circuit. The second-in-first-out circuit is sampled from the first-first-first-based circuit based on the control signal transmitted from the memory chip through the second silicon perforation. The output data of the output unit is generated by the calibration circuit based on the delay from the path of the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit. The delay control circuit is based on reading. The command and the delay code generate a control signal, and the control signal is transmitted to the memory die through the third TSV. |