| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0617
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66598 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2018-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e52f22ddc7708f90364508f97fea70d9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4780689a6c05bea61ce769bde0748e39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec5394bd0d209b138de64c4e48737087 |
| publicationDate |
2019-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201919233-A |
| titleOfInvention |
Integrated wafer and method of forming same |
| abstract |
The present disclosure relates to a transistor element in an active region. The active region has a shape configured to reduce the sensitivity of the transistor element to performance degradation (such as a kink effect) caused by a gap in an adjacent isolation structure. The transistor element has a substrate including an inner surface defining a trench within a surface above the substrate. A dielectric material is disposed in the trench. The dielectric material defines an open area that exposes the upper surface of the substrate. The open region has a source open region above a source region within the substrate, a drain open region above a drain region within the substrate, and a channel open region between the source and the drain open region. The source and drain open regions have a width smaller than the channel open region. The gate structure extends over an open area between the source and drain regions. |
| priorityDate |
2017-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |