http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201913958-A
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aea8583efc4aa4e2a9706d789804d37b |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
filingDate | 2017-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bee9ac384a600d5d601e68db4d1c9e8b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4422d45a6d24a7fae8a0660b682bc6d6 |
publicationDate | 2019-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | TW-201913958-A |
titleOfInvention | Stereo memory element and manufacturing method thereof |
abstract | A three dimensional (3D) memory component comprising: a substrate, a multi-layers stack, and a dielectric material. The substrate has at least one recess extending from the surface of the substrate into the substrate in a first direction. The multi-layer stack structure includes a plurality of conductive layers and a plurality of insulating layers staggered in a first direction and stacked on the bottom surface of the recesses. Wherein the multilayer stack structure has at least one recess passing through the conductive layer and the insulating layer in a first direction; the recess has a bottom cross-sectional dimension and an opening dimension in a vertical first direction, and the bottom cross-sectional dimension is substantially larger than the opening size. The dielectric material is at least partially filled in the recess. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I713203-B |
priorityDate | 2017-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.