http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201832241-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca748d5cbfb6d9d2f2c6013230fccd73 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0408 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-34 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34 |
| filingDate | 2014-01-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0613dd921c9d58a27a1a19801a5d2144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00135029a9a77096bd36b0d57a687400 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c00c5afa453d9f51e2fce523992694e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e6ed80acb567a74dd58d9a28d41596e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_153a3c281fc17f5f93f1559f73f06b13 |
| publicationDate | 2018-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201832241-A |
| titleOfInvention | Method for reducing program disturb in non-volatile memory cells |
| abstract | The invention provides a non-volatile memory and a method for operating the same to reduce interference. In one embodiment, the method includes coupling a first positive high voltage to a first overall word line in a first column of an array of memory cells and coupling a second negative high voltage (V NEG ). A first bit line in a first row of the array is used to apply a bias voltage to a non-volatile memory transistor in a selected memory cell in order to program the selected memory cell; a size smaller than The marginal voltage of VNEG will be coupled to a second overall word line in a second column of the array and a forbidden voltage will be coupled to a second bit line in a second row of the array for A program to reduce the bias voltage applied to a non-volatile memory transistor in an unselected memory cell, so as to reduce the program of data programmed in the unselected memory cell due to the stylized relationship. interference. |
| priorityDate | 2013-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.