| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32115 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-772 |
| filingDate |
2017-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b6b67ff1d5f7b6b4758cf36554dd7f8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c3bd9b0d4886f44d1249a24eb299e61e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4eb7e932d091d232fa180c69ede1465 |
| publicationDate |
2018-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201826401-A |
| titleOfInvention |
Method of forming a semiconductor device |
| abstract |
A method of forming a semiconductor device includes: removing a dummy gate structure on a fin structure to form a plurality of gate spaces; and forming a first layer of a conductive material in the gate space. The first layer further includes an entire structure in which the top layer is formed on the fin structure, and the gate space includes a gate space for the short channel gate and a gate space for the long channel gate. The first portion of the top layer is removed to retain the hard mask layer over the long channel gate region. A first etching step is performed to remove a portion of the height of the hard mask layer and the conductive material in the gate space for the short channel gate to form the first structure. A second layer of electrically conductive material is formed on the first structure. A second etching step is performed to remove a portion of the second layer to form a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate. |
| priorityDate |
2016-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |