| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_962adbf7d50e742218f3d536a63df612 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J11-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J11-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J201-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-26 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J11-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J11-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J201-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18 |
| filingDate |
2017-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fec481b7ef98c74252d2e171cd5252c8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ffbb78d41aa77e44c5824c866b672933 |
| publicationDate |
2018-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201803080-A |
| titleOfInvention |
Method for manufacturing plate for cubic element volume layer circuit and manufacturing method of cubic element volume layer circuit |
| abstract |
A plate 1 for manufacturing a three-dimensional multi-layered circuit, which is interposed between a plurality of semiconductor wafers having a through electrode, and is a three-dimensional element used in a three-dimensional multi-layered circuit in which the plurality of semiconductor wafers are connected to each other. The sheet 1 for manufacturing a multi-layered multilayer circuit. The above-mentioned sheet 1 for manufacturing a three-dimensional multi-layered multilayer circuit has at least a hardening adhesive layer 13 and the material constituting the adhesive layer 13 is melted at 90 ° C before hardening. The viscosity is 1.0 × 10 0 ~ 5.0 × 10 5 Pa. s. The average linear expansion coefficient of the hardened material at 0 to 130 ° C is 45 ppm or less. In such a three-dimensional multi-layered multilayer circuit manufacturing board 1, the connection resistance between semiconductor wafers is not easily changed, and a three-dimensional multi-layered multilayer circuit with high reliability can be manufactured. |
| priorityDate |
2016-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |