http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201740507-A

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filingDate 2017-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5055dccdbe2b8f716ec4f02e36ac6aba
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publicationDate 2017-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201740507-A
titleOfInvention Improved use of layout optimized switches
abstract The present invention discloses a wafer structure and a method of fabricating such a wafer structure having wiring coupled to the device structure of the high frequency switch. Forming a transistor including a first source/drain region, a second source/drain region, and a first gate electrode, the first gate electrode having a first width aligned along the first direction. A wiring step including a wire coupled to the first source/drain region is formed. The wire has a length that is aligned along a second direction that is different from the first direction.
priorityDate 2016-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 30.