| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1eb9cd2af2f87dcf20b0fbbdfe79996e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T279-34 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-463
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-4585
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-4586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-68792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6719
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-67109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-683
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-68785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-45565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-45574 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C16-54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-683 |
| filingDate |
2011-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e341554ed42858203ecd39d5bac68b49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee870a048fd61bb289a61a4148bebd0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dfd32869b3d84fc0ef794347dddb9e1d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_446624c865a13574e364baf68c7ac86c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_25e2ed45c0e7621bc79c52e1b62b06b4 |
| publicationDate |
2017-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201719801-A |
| titleOfInvention |
System and device for flowable deposition in semiconductor manufacturing |
| abstract |
Electronic device fabrication procedures, devices and systems or flowable deposition techniques for flowable gap fill are described. In some implementations, a semiconductor fabrication chamber is described that is configured to maintain a semiconductor wafer at a temperature near one of 0 ° C while maintaining most of the other components in the fabrication chamber at about 5 ° C to 10 ° C or higher than the temperature of the wafer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I797339-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I722944-B |
| priorityDate |
2010-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |