| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13067
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66348
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-36 |
| filingDate |
2014-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_878c579e06c58a69a20d961ac35d4773
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_404a7cc62e68fd4411507b653358c33d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_583073b629be771d500c8b83df736f1f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca4318f121c638d648914ebd4da36c89
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c66cb7adb389e83295bd9b6ad4836018 |
| publicationDate |
2017-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201705309-A |
| titleOfInvention |
Vertical non-planar semiconductor device for system single-chip (SoC) applications |
| abstract |
The present invention describes a vertical non-planar semiconductor device for system single-chip (SoC) applications and a method of fabricating a vertical non-planar semiconductor device. For example, a semiconductor device includes a semiconductor fin disposed over a substrate having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin between the source region and the drain region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I673779-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10847633-B2 |
| priorityDate |
2013-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |