http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201624627-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aea8583efc4aa4e2a9706d789804d37b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2015-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65cd505da0c42a0fcbdfc9a27770d09a |
| publicationDate | 2016-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201624627-A |
| titleOfInvention | Memory architecture and manufacturing method thereof |
| abstract | A memory structure comprising a vertical gate non-volatile NAND array comprising a plurality of vertically stacked NAND strings of non-volatile memory cells, a plurality of characters orthogonally arranged on a plurality of vertically stacked NAND strings a wire, and a plurality of vertical rows of conductive gate materials electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings have vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical of the plurality of vertical rows is the gate of one of the first side and the second side of the opposite side of the vertically stacked semiconductor strip. The vertical rows in the plurality of vertical rows are the gates of adjacent stacks of the plurality of vertically stacked NAND strings. |
| priorityDate | 2014-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.