http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201610996-A

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inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0575946bc60b7e4a01dada7daacd8eed
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publicationDate 2016-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201610996-A
titleOfInvention System and method involving multiple rows of dual-pipe memory circuits
abstract Multi-row dual-pipe SRAM systems, methods, procedures for operating such SRAMs, and/or methods of fabricating multi-row dual-pipe SRAMs are disclosed herein. For example, an illustrative multi-row, dual-pipe SRAM can include both read and write addresses, split and/or combined via one or more split/combining programs, and/or It is transmitted via the bus to the SRAM memory bank, wherein the read and write addresses can be read and written to a particular bank. The illustrative multi-row dual-pipe SRAM herein may also include two beats for capturing data, splitting and/or combining and combining them via one or more split/combining programs. The bus is transmitted to the features of each SRAM bank, wherein the two beats of the write data can be split/combined/reassembled via one or more programs to write the data to a particular memory bank.
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