| abstract |
The invention provides a chip package comprising a semiconductor wafer, an interposer, a polymer adhesion support layer, a first insulation layer, a redistribution line and an encapsulation layer. The semiconductor wafer has an inductive component and a conductive pad, and the conductive pad is electrically connected to the inductive component. The interposer is disposed above the semiconductor wafer and has a trench and a via, wherein the trench exposes a portion of the sensing element, and the via exposes the conductive pad. The polymer adhesion support layer is sandwiched between the semiconductor wafer and the interposer, and has an opening to expose the conductive pad. The first insulating layer is disposed on the lower surface of the interposer, and a portion of the first insulating layer is disposed in the opening to cover the polymer adhesive supporting layer. The re-layout line is disposed in the through hole to electrically connect the conductive pad. The encapsulation layer covers the interposer and the re-layout circuitry and has an opening to expose the trench. |