http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201523794-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7923 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42348 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105 |
| filingDate | 2014-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_583073b629be771d500c8b83df736f1f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_404a7cc62e68fd4411507b653358c33d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_655e20d96a53574eb8c846daad7f8310 |
| publicationDate | 2015-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201523794-A |
| titleOfInvention | Memory unit with isolated charge portion and method of manufacturing same |
| abstract | The present invention describes a memory cell having isolated charge locations and a method of fabricating a memory cell having isolated charge locations. In an example, a non-volatile charge trapping memory device includes a substrate having a channel region, a source region, and a drain region. A gate stack is disposed over the substrate over the channel region. The gate stack includes a tunneling dielectric layer disposed over the channel region, the first charge trap region, and the second charge trap region. The regions are disposed above the tunneling dielectric layer and separated by a distance. The gate stack also includes an isolation dielectric layer disposed over the tunneling dielectric layer between the first charge trapping region and the second charge trapping region. A gate dielectric layer is disposed over the first charge trapping region, the second charge trapping region, and the isolation dielectric layer. A gate electrode is disposed above the gate dielectric layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I710108-B |
| priorityDate | 2013-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.