| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_852562b0389ce75d8446afa57e94ff65 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-0651
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06506
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06562
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-49109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-73 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2014-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_036e073b27d4e77b24330247dd6587e7 |
| publicationDate |
2015-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201506934-A |
| titleOfInvention |
Asynchronous bridge chip |
| abstract |
The memory device multi-chip package assembly includes conventional parallel bus bar flash memory dies that interface with external parallel bus bars of the same format and protocol. The bridge wafer within the memory device interface internally interfaces with the flash die within the package assembly through one or more internal parallel bus bars. The bridge wafer presents a single load to the external busbar interface, allowing several memory device multi-chip package components (MCPs) to be connected to the controller to increase the flash crystal supported by a single controller channel operating at full performance The number of granules. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11544209-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I797642-B |
| priorityDate |
2013-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |