| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5685
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8836
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2013-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5b67e2da97fd009230a32fc81892613
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09ea67f852809d6bc9a9a259c2d25fd0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20dbd770c18daaadc0898fcaa5808f41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0697efbf0a3819321fb883a2ad158cf3 |
| publicationDate |
2014-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201444058-A |
| titleOfInvention |
Vertical cross-point embedded memory architecture for metal conductive metal oxide (MCOM) memory components |
| abstract |
The present invention describes a vertical cross-point embedded memory architecture for metal conductive metal oxide (MCOM) memory components. For example, a memory array includes a substrate. A plurality of horizontal word lines are disposed in a plane on the substrate. A plurality of vertical bit lines are disposed on the substrate and inserted into the plurality of horizontal word lines to provide a plurality of intersections of the word lines of the plurality of horizontal word lines and the plurality of vertical bit lines Between bit lines. A plurality of memory elements are disposed in the plane on the substrate, and a memory element is disposed at each intersection between the corresponding word line and the bit line of the intersection. |
| priorityDate |
2012-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |