http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201442244-A

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filingDate 2014-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2014-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201442244-A
titleOfInvention Enable the polysilicon gate of the spacer
abstract A spacer etch process that produces ultra-narrow polysilicon and gate oxide for an insulating gate for use with an insulated gate transistor. Dielectric channels are formed using dielectric and spacer thin film deposition techniques. The spacer film is removed from the dielectric, wherein a narrow channel is formed in the dielectric. An insulating gate oxide is grown on portions of the semiconductor substrate exposed at the bottom of the narrow channels. Next, polycrystalline germanium is used to fill the narrow channels. The dielectric is removed from the face of the semiconductor leaving only the very narrow gate oxide and the polysilicon. The very narrow gate oxide and the polysilicon are separated into insulating gates for the insulated gate transistors.
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